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LH28F400SU-NC
FEATURES
56-PIN TSOP
4M (512K x 8, 256K x 16) Flash Memory
TOP VIEW
* User-Configurable x8 or x16 Operation * 5 V Write/Erase Operation (5 V VPP)
- No Requirement for DC/DC Converter to Write/Erase
NC NC A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RP NC NC VPP RY/BY NC A17 A7 A6 A5 A4 A3 A2 A1 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
NC A16 BYTE GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE GND CE A0 NC NC
* 60 ns Maximum Access Time
(VCC = 5.0 V 0.25 V)
* 80ns Maximum Access Time
(VCC = 5.0 V 0.5 V)
* 32 Independently Lockable Blocks (16K) * 100,000 Erase Cycles per Block * Automated Byte Write/Block Erase
- Command User Interface - Status Register - RY/BY Status Output
* System Performance Enhancement
- Erase Suspend for Read - Two-Byte Write - Full Chip Erase
* Data Protection
- Hardware Erase/Write Lockout during Power Transitions - Software Erase/Write Lockout
* Independently Lockable for Write/Erase
on Each Block (Lock Block and Protect Set/Reset)
* 5 A (Typ.) ICC in CMOS Standby * 0.2 A (Typ.) Deep Power-Down * State-of-the-Art 0.45 m ETOXTM Flash
Technology
28F400SUT-NC60-1
Figure 1. 56-Pin TSOP Configuration
* 56-Pin, 1.2 mm x 14 mm x 20 mm TSOP
(Type I) Package
* 48-Pin, 1.2 mm x 12 mm x 18 mm TSOP
(Type I) Package
* 44-Pin, 600-mil SOP Package
1
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
48-PIN TSOP
TOP VIEW
44-PIN SOP VPP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RP WE A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
TOP VIEW
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RP VPP NC RY/BY NC A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE GND CE A0
RP/BY A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
28F400SUT-NC60-23
Figure 3. 44-Pin SOP Configuration
28F400SUT-NC60-24
Figure 2. 48-Pin TSOP Configuration
2
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
DQ8 - DQ15
DQ0 - DQ7
OUTPUT BUFFER
OUTPUT BUFFER
INPUT BUFFER
INPUT BUFFER
ID REGISTER
DATA QUEUE REGISTERS
I/O LOGIC
BYTE
CSR OUTPUT MULTIPLEXER REGISTER
ESRs CUI
CE OE WE RP
DATA COMPARATOR
A-1,0 - A17
INPUT BUFFER
Y-DECODER 16KB BLOCK 0
Y GATING/SENSING 16KB BLOCK 30 16KB BLOCK 31
16KB BLOCK 1
WSM
RY/BY
ADDRESS QUEUE LATCHES
...
X-DECODER
...
ADDRESS COUNTER
...
PROGRAM/ ERASE VOLTAGE SWITCH
VPP
VCC GND
28F400SUT-NC60-2
Figure 4. LH28F400SU-NC Block Diagram
3
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
PIN DESCRIPTION
SYMBOL TYPE NAME AND FUNCTION BYTE-SELECT ADDRESSES: Selects between high and low byte when device is in x8 mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the DQ15/A-1 input buffer is turned off when BYTE is high). WORD-SELECT ADDRESSES: Select a word within one 16K block. These addresses are latched during Data Writes. BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are latched during Data Writes, Erase and Lock-Block operations. LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles. Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated when the chip is de-selected or the outputs are disabled. HIGH-BYTE DATA BUS: Inputs data during x16 Data Write operations. Outputs array, buffer or identifier data in the appropriate Read mode; not used for Status register reads. Floated when the chip is de-selected or the outputs are disabled. DQ15/A-1 is address. CHIP ENABLE INPUT: Activate the device's control logic, input buffers, decoders and sense amplifiers. CE must be low to select the device. RESET/POWER-DOWN: With RP low, the device is reset, any current operation is aborted and device is put into the deep power down mode. When the power is turned on, RP pin is turned to low in order to return the device to default configuration. When the power transition is occurred, or the power on/off, RP is required to stay low in order to protect data from noise. When returning from Deep Power-Down, a recovery time of 430 ns is required to allow these circuits to power up. When RP goes low, any current or pending WSM operation(s) are terminated, and the device is reset. All Status registers return to ready (with all status flags cleared). After returning, the device is in read array mode. OUTPUT ENABLE: Gates device data through the output buffers when low. The outputs float to tri-state off when OE is high. WRITE ENABLE: Controls access to the CUI, Data Queue Registers and Address Queue Latches. WE is active low, and latches both address and data (command or array) on its rising edge. READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM is busy performing an operation. When the WSM is ready for new operation or Erase is Suspended, or the device is in deep power-down mode RY/BY pin is floated. BYTE ENABLE: BYTE low places device in x8 mode. All data is then input or output on DQ0 - DQ7, and DQ8 - DQ15 float. Address A-1 selects between the high and low byte. BYTE high places the device in x16 mode, and turns off the A-1 input buffer. Address A0, then becomes the lowest order address. ERASE/WRITE POWER SUPPLY (5.0 V 0.5 V): For erasing memory array blocks or writing words/bytes into the flash array. DEVICE POWER SUPPLY (3.3 V 0.3 V): Do not leave any power pins floating. GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating. NO CONNECT: No internal connection to die, lead may be driven or left floating.
DQ15 - A-1
INPUT
A0 - A12 A13 - A17
INPUT INPUT
DQ0 - DQ7
INPUT/OUTPUT
DQ8 - DQ15
INPUT/OUTPUT
CE
INPUT
RP
INPUT
OE
INPUT
WE
INPUT
RY /BY
OPEN DRAIN OUTPUT
BYTE
INPUT
VPP VCC GND NC
SUPPLY SUPPLY SUPPLY
4
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
INTRODUCTION
Sharp's LH28F400SU-NC 4M Flash Memory is a revolutionary architecture which enables the design of truly mobile, high performance, personal computing and communication products. With innovative capabilities, 5 V single voltage operation and very high read/write performance, the LH28F400SU-NC is also the ideal choice for designing embedded mass storage flash memory systems. The LH28F400SU-NC's independently lockable 32 symmetrical blocked architecture (16K each) extended cycling, low power operation, very fast write and read performance and selective block locking provide a highly flexible memory component suitable for cellular phone, facsimile, game, PC, printer and handy terminal. The LH28F400SU-NC's single power supply operation enables the design of memory cards which can be read/ written in 5.0 V systems. Its x8/x16 architecture allows the optimization of memory to processor interface. The flexible block locking option enables bundling of executable application software in a Resident Flash Array or memory card. Manufactured on Sharp's 0.45 m ETOXTM process technology, the LH28F400SU-NC is the most cost-effective, high-density 5.0 V flash memory.
A Superset of commands have been added to the basic LH28F008SA command-set to achieve higher write performance and provide additional capabilities. These new commands and features include:
* * * *
Software Locking of Memory Blocks Memory Protection Set/Reset Capability Two-Byte Serial Writes in 8-bit Systems Erase All Unlocked Blocks
Writing of memory data is performed typically within 13 s per byte or within 20 s per word. A Block Erase operation erases one of the 32 blocks in typically 0.6 seconds, independent of the other blocks. LH28F400SU-NC allows to erase all unlocked blocks. It is desirable in case of which you have to implement Erase operation maximum 32 times. Only in x8 mode, LH28F400SU-NC enables Two-Byte Serial Write which is operated by three times command input. Writing of memory data is performed typically within 20 s per two-byte. This feature can improve 8-bit system write performance by up to typically 10 s per byte. All operations are started by a sequence of Write commands to the device. Status Register (described in detail later) and a RY/BY output pin provide information on the progress of the requested operation. Same as the LH28F008SA, LH28F400SU-NC requires an operation to complete before the next operation can be requested, also it allows to suspend block erase to read data from any other block, and allow to resume erase operation. The LH28F400SU-NC provides user-selectable block locking to protect code or data such as Device Drivers, PCMCIA card information, ROM-Executable OS or Application Code. Each block has an associated non-volatile lock-bit which determines the lock status of the block. In addition, the LH28F400SU-NC has a software controlled master Write Protect circuit which prevents any modifications to memory blocks whose lock-bits are set. When the device power-up or RP turns High, Write Protect Set/Confirm command must be written. Otherwise, all lock bits in the device remain being locked, can't perform the Write to each block and single Block Erase. Write Protect Set/Confirm command must be written to reflect the actual lock status. However, when the device power-on or RP turns High, Erase All Unlocked Blocks can be used. If used, Erase is performed with reflecting actual lock status, and after that Write and Block Erase can be used.
DESCRIPTION
The LH28F400SU-NC is a high performance 4M (4,194,304) block erasable non-volatile random access memory organized as either 256K x 16 or 512K x 8. The LH28F400SU-NC includes thirty-two 16K (16,384) blocks. A chip memory map is shown in Figure 5. The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and results in greater product reliability and ease of use. Among the significant enhancements of the LH28F400SU-NC:
* * * * *
5 V Read, Write/Erase Operation (5 V VCC, VPP) Low Power Capability Improved Write Performance Dedicated Block Write/Erase Protection Command-Controlled Memory Protection Set/Reset Capability
A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation. Internal Algorithm Automation allows Byte Writes and Block Erase operations to be executed using a TwoWrite command sequence to the CUI in the same way as the LH28F008SA 8M Flash Memory.
5
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
The LH28F400SU-NC contains a Compatible Status Register (CSR) which is 100% compatible with the LH28F008SA Flash memory's Status Register. This register, when used alone, provides a straightforward upgrade capability to the LH28F004SUT-NC from a LH28F008SA-based design. The LH28F400SU-NC incorporates an open drain RY/BY output pin. This feature allows the user to ORtie many RY/BY pins together in a multiple memory con figuration such as a Resident Flash Array. The LH28F400SU-NC is specified for a maximum access time of 60 ns (tACC) at 5 V operation (4.75 to 5.25 V), and 70 ns (t ACC) at 5 V operation (4.5 to 5.5 V) over the commercial temperature range (0 to +70C). The LH28F400SU-NC incorporates an Automatic Power Saving (APS) feature which substantially reduces the active current when the device is in static mode of operation (addresses not switching). In APS mode, the typical ICC Current is 2 mA at 5 V. A Deep Power-Down mode of operation is invoked when the RP (called PWD on the LH28F008SA) pin transitions low, any current operation is aborted and the device is put into the deep power down mode. This mode brings the device power consumption to less than 5 A and provides additional write protection by acting as a device reset pin during power transitions. When the power is turned on, RP pin is turned to low in order to return the device to default configuration. When the power transition is occured, or at the power on/off RP pin is required to stay low in order to protect data from noise. A recovery time of 480 ns is required from RP switching high until outputs are again valid. In the Deep Power-Down State, the WSM is reset (any current operation will abort) and the CSR register is cleared. A CMOS Standby mode of operation is enabled when CE transitions high and RP stays high with all input control pins at CMOS levels. In this mode, the device draws an ICC standby current of 10 A.
MEMORY MAP
7FFFFH 7C000H 7BFFFH 78000H 77FFFH 74000H 73FFFH 70000H 6FFFFH 6C000H 6BFFFH 68000H 67FFFH 64000H 63FFFH 60000H 5FFFFH 5C000H 5BFFFH 58000H 57FFFH 54000H 53FFFH 50000H 4FFFFH 4C000H 4BFFFH 48000H 47FFFH 44000H 43FFFH 40000H 3FFFFH 3C000H 3BFFFH 38000H 37FFFH 34000H 33FFFH 30000H 2FFFFH 2C000H 2BFFFH 28000H 27FFFH 24000H 23FFFH 20000H 1FFFFH 1C000H 1BFFFH 18000H 17FFFH 14000H 13FFFH 10000H 0FFFFH 0C000H 0BFFFH 08000H 07FFFH 04000H 03FFFH 00000H
16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK 16KB BLOCK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NOTE: In Byte-wide (x8) mode A1 is the lowest order address. In Word-wide (x16) mode A1 don't care, address values are ignored A1.
28F400SUT-NC60-3
Figure 5. Memory Map
6
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS Bus Operations for Word-Wide Mode (BYTE = VIH)
MODE RP CE OE WE A0 DQ0-15 RY /BY NOTE
Read Output Disable Standby Deep Power-Down Manufacturer ID Device ID Write
VIH VIH VIH VIL VIH VIH VIH
VIL VIL VIH X VIL VIL VIL
VIL VIH X X VIL VIL VIH
VIH VIH X X VIH VIH VIL
X X X X VIL VIH X
DOUT High-Z High-Z High-Z 00B0H ID DIN
X X X VOH VOH VOH X
1, 2, 7 1, 6, 7 1, 6, 7 1, 3 4 4 1, 5, 6
Bus Operations for Byte-Wide Mode (BYTE = VIL)
MODE RP CE OE WE A0 DQ0-7 RY /BY NOTE
Read Output Disable Standby Deep Power-Down Manufacturer ID Device ID Write
VIH VIH VIH VIL VIH VIH VIH
VIL VIL VIH X VIL VIL VIL
VIL VIH X X VIL VIL VIH
VIH VIH X X VIH VIH VIL
X X X X VIL VIH X
DOUT High-Z High-Z High-Z B0H ID DIN
X X X VOH VOH VOH X
1, 2, 7 1, 6, 7 1, 6, 7 1, 3 4 4 1, 5, 6
NOTES: 1. X can be VIH or VIL for address or control pins except for RY/BY, which is either VOL or VOH . 2. RY/BY output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode, RY/BY will be at VOL if it is tied to VCC through a resistor. When the RY/BY at VOL is independent of OE while a WSM operation is in progress. 3. RP at GND 0.2 V ensures the lowest deep power-down current. 4. A0 at VIL provide manufacturer ID codes. A0 at VIH provide device ID codes. Device ID code= 21H (x8). Device ID Code = 6621H (x16). All other addresses are set to zero. 5. Commands for different Erase operations, Data Write operations, and Lock-Block operations can only be successfully completed when VPP = VPPH. 6. While the WSM is running, RY/BY in Level-Mode (default) stays at VOL until all operations are complete. RY/BY goes to VOH when the WSM is not busy or in erase suspend mode. 7. RY/BY may be at VOL while the WSM is busy performing various operations. For example, a status register read during a write operation. 8. Only to RP, VIH (MIN.) = 2.4 V at TTL-level input.
7
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
LH28F008SA-Compatible Mode Command Bus Definitions
FIRST BUS CYCLE COMMAND OPER. ADDRESS DATA OPER. ADDRESS DATA SECOND BUS CYCLE NOTE
Read Array Intelligent Identifier Read Compatible Status Register Clear Status Register Word Write Alternate Word Write Block Erase/Confirm Erase Suspend/Resume
ADDRESS AA = Array Address BA = Block Address IA = Identifier Address WA = Write Address X = Don't Care
Write Write Write Write Write Write Write Write
DATA AD = Array Data CSRD = CSR Data ID = Identifier Data WD = Write Data
X X X X X X X X
FFH 90H 70H 50H 40H 10H 20H B0H
Read Read Read
AA IA X
AD ID CSRD 1 2 3
Write Write Write Write
WA WA BA X
WD WD D0H D0H 4 4
NOTES: 1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes. 2. The CSR is automatically available after device enters Data Write, Erase or Suspend operations. 3. Clears CSR.3, CSR.4, and CSR.5. See Status register definitions. 4. While device performs Block Erase, if you issue Erase Suspend command (B0H), be sure to confirm ESS (Erase-Suspend-Status) is set to 1 on compatible status register. In the case, ESS bit was not set to 1, also completed the Erase (ESS = 0, WSMS = 1), be sure to issue Resume command (D0H) after completed next Erase command. Beside, when the Erase Suspend command is issued, while the device is not in Erase, be sure to issue Resume command (D0H) after the next erase complete.
LH28F400SU-NC Performance Enhancement Command Bus Definitions
COMMAND MODE FIRST BUS CYCLE SECOND BUS CYCLE DATA THIRD BUS CYCLE OPER. ADD. DATA NOTE
OPER. ADD. DATA OPER. ADD.
Protect Set/Confirm Protect Reset/Confirm Lock Block/Confirm Erase All Unlocked Blocks Two-Byte Write
ADDRESS BA = Block Address WA = Write Address X = Don't Care
Write Write Write Write x8 Write
X X X X X
57H 47H 77H A7H FBH
Write Write Write Write Write
0FFH 0FFH BA X A-1
D0H D0H D0H D0H WD (L, H) Write WA
1, 2 3 1, 2, 4 1, 2 WD (H, L) 1, 2, 5
DATA AD = Array Data WD (L, H) = Write Data (Low, High) WD (H, L) = Write Data (High, Low)
NOTES: 1. After initial device power-up, or return from deep power-down mode, the block lock status bits default to the locked state independent of the data in the corresponding lock bits. In order to upload the lock bit status, it requires to write Protect Set/Confirm command. 2. To reflect the actual lock-bit status, the Protect Set/Confirm command must be written after Lock Block/Confirm command. 3. When Protect Reset/Confirm command is written, all blocks can be written and erased regardless of the state of the lock-bits. 4. The Lock Block/Confirm command must be written after Protect Reset/Confirm command was written. 5. A1 is automatically complemented to load second byte of data. A1 value determines which WD is supplied first: A1 = 0 looks at the WDL, A1 = 1 looks at the WDH. In word-wide (x16) mode A1, don't care. 6. Second bus cycle address of Protect Set/Confirm and Protect Reset/Confirm command is 0FFH. Specifically A9 - A8 = 0, A7 - A0 = 1, others are don't care.
8
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
Compatible Status Register
WSMS 7 ESS 6 ES 5 DWS 4 VPPS 3 R 2 R 1 R 0
CSR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy CSR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase in Progress/Completed CSR.5 = ERASE STATUS (ES) 1 = Error in Block Erasure 0 = Successful Block Erase CSR.4 = DATA-WRITE STATUS (DWS) 1 = Error in Data Write 0 = Data Write Successful CSR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK
NOTES: 1. RY/BY output or WSMS bit must be checked to determine completion of an operation (Erase Suspend, Erase or Data Write) before the appropriate Status bit (ESS, ES or DWS) is checked for success. 2. If DWS and ES are set to `1' during an erase attempt, an improper command sequence was entered. Clear the CSR and attempt the operation again. 3. The VPPS bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates VPP's level only after the Data-Write or Erase command sequences have been entered, and informs the system if VPP has not been switched on. VPPS is not guaranteed to report accurate feedback between VPPL and VPPH. 4. CSR.2 - CSR.0 = Reserved for further enhancements. These bits are reserved for future use and should be masked out when polling the CSR.
4M FLASH MEMORY SOFTWARE ALGORITHMS Overview
With the advanced Command User Interface, its Performance Enhancement commands and Status Registers, the software code required to perform a given operation may become more intensive but it will result in much higher write/erase performance compared with current flash memory architectures. The software flowcharts describing how a given operation proceeds are shown here. Figures 4 through 6 depict flowcharts using the 2nd generation flash device in the LH28F008SA-compatible mode. Figures 7 through 12 depict flowcharts using the 2nd generation flash device's performance enhancement commands mode. When the device power-up or the device is reset by RP pin, all blocks come up locked. Therefore, Word/ Byte Write, Two Byte Serial Write and Block Erase can not be performed in each block. However, at that time, Erase All Unlocked Block is performed normally, if used, and reflect actual lock status, also the unlocked block data is erased. When the device power-up or the device is reset by RP pin, Set Write Protect command must be written to reflect actual block lock status. Reset Write Protect command must be written before Write Block Lock command. To reflect actual block lock status, Set Write Protect command is succeeded.
The Compatible Status Register (CSR) is used to determine which blocks are locked. In order to see Lock Status of a certain block, a Word/Byte Write command (WA = Block Address, WD = FHH) is written to the CUI, after issuing Set Write Protect command. If CSR.7, CSR.5 and CSR.4 (WSMS, ES and DWS) are set to '1's, the block is locked. If CSR.7 is set to '1', the block is not locked. Reset Write Protect command enables Write/Erase operation to each block. In the case of Block Erase is performed, the block lock information is also erased. Block Lock command and Set Write Protect command must be written to prohibit Write/Erase operation to each block. There are unassigned commands. It is not recommended that the customer use any command other than the valid commands specified in "Command Bus Definitions". Sharp reserved the right to redefine these codes for future functions. Please do not execute reprogramming 0 for the bit which has already been programmed 0. Overwrite operation may generate unerasable bit. In case of reprogramming 0 to the Byte data which has been programmed 1. * Program 0 for the bit in which you want to change data from 1 to 0. * Program 1 for the bit which has already been programmed 0. For example, changing Byte data from 10111101 to 10111100 requires 11111110 programming.
9
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
START
BUS OPERATION
COMMAND
COMMENTS
WRITE 40H or 10H
Write Write
Word/Byte Write
D = 40H or 10H A=X D = WD A = WA Q = CSRD Toggle CE or OE to update CSRD. A=X Check CSR.7 1 = WSM Ready 0 = WSM Busy
WRITE DATA/ADDRESS
Read
READ COMPATIBLE STATUS REGISTER
Standby
0
CSR.7 =
1 CSR FULL STATUS CHECK IF DESIRED
Repeat for subsequent Word/Byte Writes. CSR Full Status Check can be done after each Word/Byte Write, or after a sequence of Word/Byte Writes. Write FFH after the last operation to reset device to read array mode. See Command Bus Cycle notes for description of codes.
OPERATION COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD (see above)
BUS OPERATION
COMMAND
COMMENTS
Standby
0 DATA WRITE SUCCESSFUL
Check CSR.4, 5 1 = Data Write Unsuccessful 0 = Data Write Successful Check CSR.3 1 = VPP Low Detect 0 = VPP OK
CSR.4, 5 =
Standby
1
CSR.3 =
1
VPP LOW DETECT
CSR.3, 4, 5 should be cleared, if set, before further attempts are initiated.
0 CLEAR CSRD RETRY/ERROR RECOVERY
28F400SUT-NC60-4
Figure 6. Word/Byte Writes with Compatible Status Register
10
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
START
BUS OPERATION
COMMAND
COMMENTS
WRITE 20H
Write Write
Block Erase Confirm
D = 20H A=X D = D0H A = BA Q = CSRD Toggle CE or OE to update CSRD. A=X Check CSR.7 1 = WSM Ready 0 = WSM Busy
WRITE D0H AND BLOCK ADDRESS
Read
READ COMPATIBLE STATUS REGISTER SUSPEND NO ERASE LOOP SUSPEND YES ERASE
Standby
CSR.7 =
0
1 CSR FULL STATUS CHECK IF DESIRED
Repeat for subsequent Block Erasures. CSR Full Status Check can be done after each Block Erase, or after a sequence of Block Erasures. Write FFH after the last operation to reset device to read array mode. See Command Bus Cycle notes for description of codes.
OPERATION COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD (see above) BUS OPERATION COMMAND COMMENTS
Standby
0 ERASE SUCCESSFUL
CSR.4, 5 =
Check CSR.4, 5 1 = Erase Error 0 = Erase Successful Both 1 = Command Sequence Error Check CSR.3 1 = VPP Low Detect 0 = VPP OK
1
Standby
CSR.3 =
1
VPP LOW DETECT
0 CLEAR CSRD RETRY/ERROR RECOVERY (NOTE)
CSR.3, 4, 5 should be cleared, if set, before further attempts are initiated. NOTE: If CSR.3 (VPPS) is set to '1', after clearing CSR.3/4/5, 1. Issue Reset WP command. 2. Retry Single Block Erase command. 3. Set WP command is issued, if necessary. If CSR.3 (VPPS) is set to '0', after clearing CSR.3/4/5, 1. Retry Single Block Erase command. If power is off or RP is low during erase operation, 1. Clear CSR.3/4/5 and issue Reset WP command, 2. Retry Single Block Erase command. 3. Set WP command is issued, if necessary.
28F400SUT-NC60-5
Figure 7. Block Erase with Compatible Status Register
11
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
START
BUS OPERATION
COMMAND
COMMENTS
WRITE B0H
Write Read
Erase Suspend
D = B0H A=X Q = CSRD Toggle CE or OE to update CSRD. A=X Check CSR.7 1 = WSM Ready 0 = WSM Busy Check CSR.6 1 = Erase Suspended 0 = Erase Completed
READ COMPATIBLE STATUS REGISTER
Standby
CSR.7 = 0
1
Standby
CSR.6 =
0
Write
ERASE COMPLETED
Read Array
D = FFH A=X Q = AD Read must be from block other than the one suspended.
1 WRITE FFH
Read
Write
READ ARRAY DATA
Erase Resume
D = D0H A=X
See Command Bus Cycle notes for description of codes. DONE NO READING?
YES WRITE D0H WRITE FFH
ERASE RESUMED
READ ARRAY DATA
28F400SUT-NC60-6
Figure 8. Erase Suspend to Read Array with Compatible Status Register
12
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
START
BUS COMMAND OPERATION
COMMENTS
READ COMPATIBLE STATUS REGISTER
Read
Q = CSRD Toggle CE or OE to update CSRD. 1 = WSM Ready 0 = WSM Busy Reset Write Protect After Write D = 47H A = X, Write D = D0H A = 0FFH Q = CSRD Toggle CE or OE to update CSRD. 1 = WSM Ready 0 = WSM Busy Lock Block Confirm D = 77H A=X D = D0H A = BA Q = CSRD Toggle CE or OE to update CSRD. 1 = WSM Ready 0 = WSM Busy Set Write Protect After Write D = 57H A = X, Write D = D0H A = 0FFH
CSR.7 =
0
Write Read
1 RESET WP
READ COMPATIBLE STATUS REGISTER
Write Write
CSR.7 =
0
Read
1 WRITE 77H
Write
WRITE D0H AND BLOCK ADDRESS
READ COMPATIBLE STATUS REGISTER
NOTE: See CSR Full Status Check for Data-Write operation. If CSR.4, 5 is set, as it is command sequence error, should be cleared before further attempts are initiated. Write FFH after the last operation to reset device to read array mode. See Command Bus Definitions for description of codes.
CSR.7 =
0
1
CSR.4, 5 =
1
(NOTE)
0 LOCK ANOTHER BLOCK? NO SET WP
YES
OPERATION COMPLETE
28F400SUT-NC60-7
Figure 9. Block Locking Scheme
13
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
START
START
RESET WP (NOTE 1)
RESET WP (NOTE 1)
ERASE BLOCK (NOTE 2)
WRITE MORE DATA TO BLOCK (NOTE 4)
SET WP (NOTE 3)
SET WP (NOTE 3)
WRITE NEW DATA TO BLOCK (NOTE 4)
OPERATION COMPLETE FLOW TO ADD DATA
RELOCK BLOCK (NOTE 5)
OPERATION COMPLETE FLOW TO REWRITE DATA NOTES: 1. Use Reset-Write-Protect flowchart. Enable Write/Erase operation to all blocks. 2. Use Block-Erase flowchart. Erasing a block clears any previously established lockout for that block. 3. Use Set-Write-Protect flowchart. This step re-implements protection to locked blocks. 4. Use Word/Byte-Write or 2-Byte-Write flowchart sequences to write data. 5. Use Block-Lock flowchart to write lock bit if desired.
28F400SUT-NC60-8
Figure 10. Updating Data in a Locked Block
14
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
START
(Apply to LH28F400SU, x16/x8, 48TSOP/56TSOP/44SOP)
BUS COMMAND OPERATION COMMENTS
READ COMPATIBLE STATUS REGISTER
Read
CSR.7 =
0
Q = CSRD Toggle CE or OE to update CSRD. 1 = WSM Ready 0 = WSM Busy 2-Byte Write D = FBH A=X D = WD A-1 = 0 loads low byte of Data Register. A-1 = 1 loads high byte of Data Register. Other Addresses = X D = WD A = WA Internally, A-1 is automatically complemented to load the alternate byte location of the Data Register. Q = CSRD Toggle CE or OE to update CSRD. 1 = WSM Ready 0 = WSM Busy
Write
1
Write
WRITE FBH
WRITE DATA/A-1
WRITE DATA/ADDRESS
Write
READ COMPATIBLE STATUS REGISTER
Read
0
CSR.7 =
1
CSR.4, 5 =
1
(NOTE)
0
NOTE: If CSR.4, 5 is set, as it is command sequence error, should be cleared before further attempts are initiated. CSR Full Status Check can be done after each 2-Byte Write, or after a sequence of 2-Byte Writes. Write FFH after the last operation to reset device to read array mode. See Command Bus Cycle notes for description of codes.
ANOTHER 2-BYTE WRITE NO
YES
OPERATION COMPLETE
28F400SUT-NC60-9
Figure 11. Two-Byte Serial Writes with Compatible Status Registers (LH28F400SU)
15
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
START (NOTE)
BUS OPERATION
COMMAND
COMMENTS
Write
WRITE A7H
Erase All Unlocked Blocks Confirm
D = A7H A=X D = D0H A=X Q = CSRD Toggle CE or OE to update CSRD A=X Check CSR.7 1 = WSM Ready 0 = WSM Busy
WRITE D0H
Write Read
READ COMPATIBLE STATUS REGISTER SUSPEND NO ERASE LOOP 0 YES
Standby
CSR.7 =
SUSPEND ERASE
1 CSR FULL STATUS CHECK IF DESIRED
CSR Full Status Check can be done after Erase All Unlocked Block, or after a sequence of Erasures. Write FFH after the last operation to reset device to read array mode. See Command Bus Cycle notes for description of codes. NOTE: Where power off or RP is set low during erase operation, 1. Clear CSR.3/4/5 and issue Reset WP command, 2. Retry Erase All Unlocked Block Erase command to erase all blocks, or issue Single Block Erase to erase all of the unlocked blocks in sequence. 3. Set WP command is issued, if necessary.
OPERATION COMPLETE
CSR FULL STATUS CHECK PROCEDURE
READ CSRD (see above)
BUS OPERATION
COMMAND
COMMENTS
Standby
CSR.4, 5 =
0
ERASE SUCCESSFUL
Check CSR.4, 5 1 = Erase Error 0 = Erase Successful Both 1 = Command Sequence Error Check CSR.3 1 = VPP Low Detect 0 = VPP OK
Standby
1
CSR.3 =
1
VPP LOW DETECT
CSR.3, 4, 5 should be cleared, if set, before further attempts are initiated. NOTE: If CSR.3 (VPPS) is set to '1', after clearing CSR.3/4/5, 1. Issue Reset WP command, 2. Retry Erase All Unlocked Block Erase command to erase all blocks, or issue Single Block Erase to erase all of the unlocked blocks in sequence. 3. Set WP command is issued, if necessary. If CSR.3 (VPPS) is set to '0', after clearing CSR.3/4/5, 1. Retry Erase All Unlocked Block Erase command.
0 CLEAR CSRD RETRY/ERROR RECOVERY (NOTE)
28F400SUT-NC60-10
Figure 12. Erase All Unlocked Blocks with Compatible Status Registers
16
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
START
BUS COMMAND OPERATION
COMMENTS
Read
READ COMPATIBLE STATUS REGISTER
Check CSR.7 1 = WSM Ready 0 = WSM Busy Set Write Protect Set Confirm D = 57H A=X D = D0H A = 0FFH (A9 - A8 = 0, A7 - A0 = 1, Others = X) Check CSR.7 1 = WSM Ready 0 = WSM Busy Check CSR.4, 5 1 = Unsuccesful 0 = Successful
Write Write
CSR.7 =
0
1
Read
WRITE 57H
Read
WRITE CONFIRM DATA/ADDRESS
READ COMPATIBLE STATUS REGISTER
CSR.7 =
0
NOTE: If CSR.4, 5 is set, as it is command sequence error, should be cleared before further attempts are initiated. Upon device power-up or toggle RP, Set Write Protect command must be written to reflect the actual lock-bit status. Write FFH after the last operation to reset device to Read Array Mode. See Command Bus Cycle notes for description of codes.
1
CSR.4, 5 =
1
(NOTE)
0 OPERATION COMPLETE
28F400SUT-NC60-11
Figure 13. Set Write Protect
17
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
START
BUS COMMAND OPERATION
COMMENTS
Read
READ COMPATIBLE STATUS REGISTER
Check CSR.7 1 = WSM Ready 0 = WSM Busy Reset Write Protect Reset Confirm D = 47H A=X D = D0H A = 0FFH (A9 - A8 = 0, A7 - A0 = 1, Others = X) Check CSR.7 1 = WSM Ready 0 = WSM Busy Check CSR.4, 5 1 = Unsuccesful 0 = Successful
Write Write
CSR.7 =
0
1
Read
WRITE 47H
Read
WRITE CONFIRM DATA/ADDRESS
READ COMPATIBLE STATUS REGISTER
CSR.7 =
0
NOTE: If CSR.4, 5 is set, as it is command sequence error, should be cleared before further attempts are initiated. Reset Write Protect command enables Write/Erase operation to all blocks. Write FFH after the last operation to reset device to Read Array Mode. See Command Bus Cycle notes for description of codes.
1
CSR.4, 5 =
1
(NOTE)
0 OPERATION COMPLETE
28F400SUT-NC60-12
Figure 14. Reset Write Protect
18
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings*
Temperature under bias ......................... 0C to +80C Storage temperature ......................... -65C to +125C
*WARNING: Stressing the device beyond
the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
VCC = 5.0 V 0.5 V Systems
SYMBOL PARAMETER MIN. MAX. UNITS TEST CONDITIONS NOTE
TA VCC VPP V I IOUT
Operating Temperature, Commercial VCC with Respect to GND VPP Supply Voltage with Respect to GND Voltage on any Pin (Except VCC, VPP) with Respect to GND Current into any Non-Supply Pin Output Short Circuit Current
0 -0.2 -0.2 -0.5
70.0 7.0 7.0 7.0 30 100.0
C V V V mA mA
Ambient Temperature
1 2 2 2
3
NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins is VCC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time.
Capacitance For 5.0 V Systems
SYMBOL PARAMETER TYP. MAX. UNITS TEST CONDITIONS NOTE
Capacitance Looking into an Address/Control Pin CIN Capacitance Looking into an Address/Control Pin A1 Capacitance Looking into an Output Pin Load Capacitance Driven by Outputs for Timing Specifications Equivalent Testing Load Circuit VCC 10%
NOTE: 1. Sampled, not 100% tested.
7 9 9
10 12 12 100 2.5
pF pF pF pF ns
TA = 25C, f = 1.0 MHz TA = 25C, f = 1.0 MHz TA = 25C, f = 1.0 MHz For VCC = 5.0 V 0.5 V 25 transmission line delay
1 1 1 1
COUT CLOAD
19
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
Timing Nomenclature
For 5.0 V systems use the standard JEDEC cross point definitions. Each timing parameter consists of 5 characters. Some common examples are defined below: tCE tOE tAS tDH tELQV tGLQV time (t) from CE (E) going low (L) to the outputs (Q) becoming valid (V) time (t) from OE (G) going low (L) to the outputs (Q) becoming valid (V) time (t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tACC tAVQV
tAVWH time (t) from address (A) valid (V) to WE (W) going high (H) tWHDX time (t) from WE (W) going high (H) to when the data (D) can become undefined (X)
PIN CHARACTERS PIN STATES
A D Q E G W P R V 5V
Address Inputs Data Inputs Data Outputs CE (Chip Enable) OE (Output Enable) WE (Write Enable) RP (Deep Power-Down Pin) RY /BY (Ready/Busy) Any Voltage Level VCC at 4.5 V Min.
H L V X Z
High Low Valid Driven, but not necessarily valid High Impedance
2.4 INPUT 0.45
2.0 0.8
TEST POINTS
2.0 0.8
2.5 ns OF 25 TRANSMISSION LINE OUTPUT FROM OUTPUT UNDER TEST TEST POINT
NOTE: AC test inputs are driven at VOH (2.4 VTTL) for a Logic '1' and VOL (0.45 VTTL) for a Logic '0'. Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns.
TOTAL CAPACITANCE = 100 pF
28F400SUT-NC60-15
28F400SUT-NC60-13
Figure 15. Transient Input/Output Reference Waveform (VCC = 5.0 V 0.5 V)
Figure 17. Transient Equivalent Testing Load Circuit (VCC = 5.0 V 0.5 V)
3.0 INPUT 1.5 0.0 TEST POINTS 1.5 OUTPUT
FROM OUTPUT UNDER TEST
2.5 ns OF 83 TRANSMISSION LINE TEST POINT
NOTE: AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a Logic '0'. Input timing begins, and output timing ends at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns.
28F400SUT-NC60-14
TOTAL CAPACITANCE = 30 pF
28F400SUT-NC60-16
Figure 16. Transient Input/Output Reference Waveform (VCC = 5.0 V .25 V) 20
Figure 18. Transient Equivalent Testing Load Circuit (VCC = 5.0 V .25 V)
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
DC Characteristics
VCC = 5.0 V 0.5 V, TA = 0C to +70C
SYMBOL PARAMETER TYP. MIN. MAX. UNITS TEST CONDITIONS NOTE
IIL ILO
Input Load Current Output Leakage Current 5
1 10 10
A A A
VCC = VCC MAX., VIN = VCC or GND VCC = VCC MAX., VIN = VCC or GND VCC = VCC MAX., CE , RP = VCC 0.2 V BYTE = VCC 0.2 V or GND 0.2 V VCC = VCC MAX., CE , RP = VIH BYTE = VIH or VIL RP = GND 0.2 V VCC = VCC MAX., CMOS: CE = GND 0.2 V BYTE = GND 0.2 V or VCC 0.2 V Inputs = GND 0.2 V or VCC 0.2 V TTL: CE = VIL, BYTE = VIL or VIH Inputs = VIL or VIH f = 10 MHz, IOUT = 0 mA
1 1
ICCS
VCC Standby Current 1 VCC Deep Power-Down Current 4 mA
1, 4
ICCD
0.2
5
A
1
ICCR1
VCC Read Current
60
mA
1, 3, 4
ICCR2
VCC Read Current
16
30
mA
VCC = VCC MAX., CMOS: CE = GND 0.2 V BYTE = VCC 0.2 V or GND 0.2 V Inputs = GND 0.2 V or VCC 0.2 V 1, 3, 4 TTL: CE = VIL, BYTE = VIH or VIL Inputs = VIL or VIH, f = 5 MHz, IOUT = 0 mA Word/Byte Write in Progress Block Erase in Progress CE = VIH Block Erase Suspended VPP VCC RP = GND 0.2 V 1 1 1, 2 1 1
ICCW ICCE ICCES IPPS IPPD
VCC Write Current VCC Block Erase Current VCC Erase Suspend Current VPP Standby Current VPP Deep Power-Down Current
18 18 5 1 0.2
35 25 10 10 5
mA mA mA A A
21
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
DC Characteristics (Continued)
VCC = 5.0 V 0.5 V, TA = 0C to +70C
SYMBOL PARAMETER TYP. MIN. MAX. UNITS TEST CONDITIONS NOTE
IPPR IPPW IPPE IPPES VIL VIH VOL VOH1
VPP Read Current VPP Write Current VPP Erase Current VPP Erase Suspend Current Input Low Voltage Input High Voltage Output Low Voltage 0.85 VCC Output High Voltage VCC - 0.4 VPP during Normal Operations VPP during Write/Erase Operations VCC Erase/Write Lock Voltage 5.0 0.0 4.5 1.4 15 20 65 -0.5 2.0
200 35 40 200 0.8 VCC + 0.5 0.45
A mA mA A V V V V V
VPP > VCC VPP = VPPH, Word/Byte Write in Progress VPP = VPPH, Block Erase in Progress VPP = VPPH, Block Erase Suspended
1 1 1 1
5 VCC = VCC MIN. and IOL = 5.8 mA IOH = 2.5 mA VCC = VCC MIN. IOH = 100 A VCC = VCC MIN.
VOH
2
VPPL VPPH VLKO
5.5 5.5
V V V
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 5.0 V, T = 25C. These currents are valid for all product versions (package and speeds). 2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Automatic Power Saving (APS) reduces ICCR to less than 2 mA in Static operation. 4. CMOS inputs are either VCC 0.2 V or GND 0.2 V. TTL Inputs are either VIL or VIH. 5. Only to RP, VIH (MIN.) = 2.4 V at VTTL-level input.
22
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
AC Characteristics - Read Only Operations1
VCC = 5.0 V 0.5 V, TA = 0C to +70C
VCC = 5.0 V 0.25 V VCC = 5.0 V 0.5 V MIN. MAX. MIN.
70 0
SYMBOL
PARAMETER
UNITS
NOTE
MAX.
tAVAV tAVGL tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH tFLGZ tFLEL tFHEL
Read Cycle Time Address Setup to OE Going Low Address to Output Delay CE to Output Delay RP High to Output Delay OE to Output Delay CE to Output in Low Z CE to Output in High Z OE to Output in Low Z OE to Output in High Z Output Hold from Address, CE or OE change, whichever occurs first BYTE Low to Output in High Z BYTE High or Low to CE Low
60 0 60 60 400 30 0 25 0 25 0 40 15
ns ns
70 70 430 35
3
ns ns ns ns ns 2 3 3 3 3 3 3 3 2
0 30 0 30 0 45 15
ns ns ns ns ns ns
NOTES: 1. See AC Input/Output Reference Waveforms for timing measurements. 2. OE may be delayed up to t ELQV - tGLQV after the falling edge of CE without impact on tELQV. 3. Sampled, not 100% tested. 4. Only to RP, VIH (MIN.) = 2.4 V.
23
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
VCC POWER-UP
STANDBY
DEVICE AND ADDRESS SELECTION
OUTPUTS ENABLED
DATA VALID
ADDRESSES (A)
VIH VIL
ADDRESSES STABLE tAVAV
... ...
VCC STANDBY POWER-DOWN
CE (E)
VIH VIL
...
tEHQZ
OE (G)
VIH VIL tAVGL VIH VIL tGLQV tELQV tGLQX tELQX VOH VOL tAVQV 5.0 V HIGH-Z tOH
...
tGHQZ
...
WE (W)
...
VALID OUTPUT
DATA (D/Q)
HIGH-Z
...
VCC
GND tPHQV VIH VIL
28F400SUT-NC60-17
RP (P)
Figure 19. Read Timing Waveforms
24
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
ADDRESSES (A)
VIH VIL
...
ADDRESSES STABLE tAVAV
...
CE (E)
VIH VIL
...
tEHQZ
OE (G)
VIH VIL tFLEL tAVGL tAVQV VIH VIL tGLQV tELQV tGLQX tELQX VOH VOL tAVQV tFLQZ VOH VOL HIGH-Z HIGH-Z HIGH-Z tOH
...
tGHQZ
BYTE (F)
...
...
DATA OUTPUT
DATA (DQ0 - DQ7)
...
DATA OUTPUT
HIGH-Z
DATA (DQ8 - DQ15)
DATA OUTPUT
28F400SUT-NC60-18
Figure 20. BYTE Timing Waveforms
25
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
POWER-UP AND RESET TIMINGS
VCC POWER UP RP (P) 5.0 V 4.5 V VCC (5 V) 0V
tPL5V
ADDRESS (A) tAVQV
VALID
DATA (Q) tPHQV
VALID 5.0 V OUTPUTS
28F400SUT-NC60-19
Figure 21. VCC Power-Up and RP Reset Waveforms
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
NOTE
tPL5V tAVQV tPHQV
RP Low to VCC at 4.5 V MIN. Address Valid to Data Valid for VCC = 5 V 10% RP High to Data Valid for VCC = 5 V 10%
0 75 430
s ns ns
1 2 2
NOTES: CE and OE are switched low after Power-Up. 1. The power supply may start to switch concurrently with RP going Low. RP is required to stay low, until VCC stays at recommended operating voltage. 2. The address access time and RP high to data valid time are shown for 5.0 V VCC operation. Refer to the AC Characteristics Read Only Operations also.
26
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
AC Characteristics for WE - Controlled Command Write Operations1
VCC = 5.0 V 0.5 V, TA = 0C to +70C
SYMBOL PARAMETER TYP. VCC = 5.0 V 0.25 V VCC = 5.0 V 0.5 V MIN. MAX. MIN.
70
UNITS
NOTE
MAX.
tAVAV tVPWH tPHEL tELWL tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tGHWL tWHRL tRHPL tPHWL tWHGL tQVVL tWHQV1 tWHQV2
Write Cycle Time VPP Set up to WE Going High RP Setup to CE Going Low CE Setup to WE Going Low Address Setup to WE Going High Data Setup to WE Going High WE Pulse Width Data Hold from WE High Address Hold from WE High CE Hold from WE High WE Pulse Width High Read Recovery before Write WE High to RY /BY Going Low RP Hold from Valid Status Register Data and RY /BY High RP High Recovery to WE Going Low Write Recovery before Read VPP Hold from Valid Status Register Data and RY /BY High Duration of Byte Write Operation Duration of Block Erase Operation 13
60
ns ns ns ns ns ns ns ns ns ns ns ns
100
100 400 0 55 55 55 0 10 10 30 0 100 0 1 60 0 4.5 0.3
100 430 0 60 60 60 0 10 10 30 0
3
2, 6 2, 6
2 2
ns ns s ns s s s 4, 5 4 3
0 1 65 0 4.5 0.3
NOTES: 1. Read timing during write and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. 4. Write/Erase durations are measured to valid Status Register (CSR) Data. 5. Byte write operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of WE for all Command Write operations.
27
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
DEEP POWER-DOWN
WRITE VALID WRITE ADDRESS AND DATA DATA-WRITE (DATA-WRITE) OR OR ERASE ERASE CONFIRM SETUP COMMAND COMMAND
AUTOMATED DATA-WRITE OR ERASE DELAY
ADDRESSES (A) VIH (NOTE 1) VIL tAVAV ADDRESSES (A) VIH (NOTE 2) VIL tAVAV VIH VIL tWHEH tELWL VIH VIL tWHWL VIH VIL tWLWH tWHDX tDVWH DATA (D/Q) VIH VIL tPHWL VOH VOL HIGH-Z DIN
AIN tAVWH tWHAX AIN tAVWH tWHAX (NOTE 3)
READ COMPATIBLE STATUS REGISTER DATA
CE (E)
tWHGL
OE (G)
tWHQV 1, 2
tGHWL
WE (W)
DIN tWHRL
DIN
DOUT
DIN
RY/BY (R)
tRHPL VIH VIL tVPWH VPPH VPP (V) V PPL NOTES: 1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD. 2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations. 4. RP low transition is only to show tRHPL; not valid for above Read and Write cycles. tQVVL
RP (P)
(NOTE 4)
28F400SUT-NC60-20
Figure 22. AC Waveforms for Command Write Operations
28
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
AC Characteristics for CE - Controlled Command Write Operations1
VCC = 5.0 V 0.5 V, TA = 0C to +70C
SYMBOL PARAMETER TYP. VCC = 5.0 V 0.25 V VCC = 5.0 V 0.5 V MIN. MAX. MIN.
70
UNITS
NOTE
MAX.
tAVAV tPHWL tVPEH tWLEL tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tGHEL tEHRL tRHPL tPHEL tEHGL tQVVL tEHQV1 tEHQV2
Write Cycle Time RP Setup to WE Going Low VPP Set up to CE Going High WE Setup to CE Going Low Address Setup to CE Going High Data Setup to CE Going High CE Pulse Width Data Hold from CE High Address Hold from CE High WE Hold from CE High CE Pulse Width High Read Recovery before Write CE High to RY /BY Going Low RP Hold from Valid Status Register Data and RY /BY High RP High Recovery to CE Going Low Write Recovery before Read VPP Hold from Valid Status Register Data and RY /BY High Duration of Byte Write Operation Duration of Block Erase Operation
13
60
ns ns ns ns ns ns ns ns ns ns ns ns
100
400 100 0 55 55 55 0 10 10 30 0 100 0 1 60 0 4.5 0.3
430 100 0
60
3
3
2, 6 2, 6
60 60 0 10 10 30 0
2 2
ns ns s ns s s s 4, 5 4 3
0 1 65 0 4.5 0.3
NOTES: 1. Read timing during write and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, but not 100% tested. 4. Write/Erase durations are measured to valid Status Register (CSR) Data. 5. Byte Write operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of CE for all Command Write operations.
29
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
DEEP POWER-DOWN
WRITE VALID WRITE ADDRESS AND DATA DATA-WRITE (DATA-WRITE) OR OR ERASE ERASE CONFIRM SETUP COMMAND COMMAND
AUTOMATED DATA-WRITE OR ERASE DELAY
ADDRESSES (A) (NOTE 1)
VIH VIL tAVAV VIH VIL tAVAV VIH VIL tEHWH tWLEL VIH VIL tEHEL VIH VIL tELEH tEHDX tDVEH
AIN tAVEH tEHAX (NOTE 3)
READ COMPATIBLE STATUS REGISTER DATA
ADDRESSES (A) (NOTE 2)
AIN tAVEH tEHAX
WE (W)
tEHGL
OE (G)
tEHQV 1, 2
tGHEL
CE (E)
DATA (D/Q)
VIH VIL
HIGH-Z tPHEL
DIN
DIN tEHRL
DIN
DOUT
DIN
RY/BY (R)
VOH VOL tRHPL VIH VIL tVPEH VPPH VPPL
RP (P)
(NOTE 4) tQVVL
VPP (V)
NOTES: 1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD. 2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD. 3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations. 4. RP low transition is only to show tRHPL; not valid for above Read and Write cycles.
28F400SUT-NC60-21
Figure 23. Alternate AC Waveforms for Command Write Operations
30
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
Erase and Byte Write Performance
VCC = 5.0 V 0.5 V, TA = 0C to +70C
SYMBOL PARAMETER TYP.(1) MIN. MAX. UNITS TEST CONDITIONS NOTE
tWHRH1 tWHRH2 tWHRH3 tWHRH4 tWHRH5 tWHRH5
Byte Write Time Two-Byte Serial Write Time Word Write Time 16KB Block Write Time 16KB Block Write Time 16KB Block Write Time Block Erase Time (16KB) Full Chip Erase Time
13 20 20 0.22 0.17 0.17 0.6 8.8 - 14.4 1.0 1.0 1.0 10
s s s s s s s s Byte Write Mode Two-Byte Serial Write Mode Word Write Mode
2 2, 3 2, 4 2 2, 3 2, 4 2 2, 5
NOTES: 1. 25C, VPP = 5.0 V Sampled. 2. Excludes System-Level Overhead. 3. Two-Byte Serial Write mode is valid at x8-bit configuration only. 4. Word Write mode is valid at x16-bit configuration only. 5. Depends on the number of protected blocks.
31
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
56TSOP (TSOP056-P-1420)
1 56
0.50 [0.020] TYP.
0.28 [0.011] 0.12 [0.005] 28 29
0.13 [0.005] 0.49 [0.019] 0.39 [0.015] 20.30 [0.799] 19.70 [0.776] 18.60 [0.732] 18.20 [0.717] 0.18 [0.007] 0.08 [0.003] PACKAGE BASE PLANE 19.30 [0.760] 18.70 [0.736] MAXIMUM LIMIT MINIMUM LIMIT 0.22 [0.009] 0.02 [0.001] 1.10 [0.043] 0.90 [0.035] 1.19 [0.047] MAX.
DIMENSIONS IN MM [INCHES]
14.20 [0.559] 13.80 [0.543]
56TSOP
32
4M (512K x 8, 256K x 16) Flash Memory
LH28F400SU-NC
48TSOP (TSOP048-P-1218)
0.50 [0.020] TYP. 48 0.30 [0.012] 0.10 [0.004] 25
16.60 [0.654] 16.20 [0.638]
18.40 [0.724] 17.60 [0.693]
17.00 [0.669]
1 12.20 [0.480] 11.80 [0.465]
24 0.20 [0.008] 0.10 [0.004] 1.10 [0.043] 0.90 [0.035] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000]
0.15 [0.006] 0.425 [0.017]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
48TSOP
33
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
44SOP (SOP044-P-0600)
1.27 [0.050] TYP.
0.50 [0.020] 0.30 [0.012]
44
23
13.40 [0.528] 13.00 [0.512]
16.40 [0.646] 15.60 [0.614]
14.40 [0.567]
1 28.40 [1.118] 28.00 [1.102]
22
SEE DETAIL 0.20 [0.008] 0.10 [0.004] 2.9 [0.114] 2.5 [0.098]
DETAIL
0.15 [0.006] 1.275 [0.050] 2.9 [0.114] 2.5 [0.098] 0.25 [0.010] 0.05 [0.002] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 3.25 [0.128] 2.45 [0.096] 0.25 [0.010] 0.05 [0.002]
1.275 [0.050]
0 - 10 0.80 [0.031]
44SOP
ORDERING INFORMATION
LH28F400SU Device Type X Package -NC## Speed 60 (VCC = 5.0 V 0.25 V) Access Time (ns) 80 (VCC = 5.0 V 0.50 V) T 56-pin, 1.2 mm x 14 mm x 20 mm TSOP (Type I) (TSOP056-P-1420) E 48-pin, 1.2 mm x 12 mm x 18 mm TSOP (Type I) (TSOP048-P-1218) N 44-pin, 600-mil SOP (SOP044-P-0600) 4M (512K x 8, 256K x 16) Flash Memory Example: LH28F400SUT-NC60 (4M (512K x 8, 256K x 16) Flash Memory, 60 ns, 56-pin TSOP)
28F400SUT-NC60-22
34
LH28F400SU-NC
4M (512K x 8, 256K x 16) Flash Memory
LIFE SUPPORT POLICY SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation. WARRANTY SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY EXCLUDED. SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied.
(R)
NORTH AMERICA
EUROPE
ASIA
SHARP Electronics Corporation Microelectronics Group 5700 NW Pacific Rim Blvd., M/S 20 Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Telex: 49608472 (SHARPCAM) Facsimile: (360) 834-8903 http://www.sharpmeg.com
SHARP Electronics (Europe) GmbH Microelectronics Division Sonninstrae 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Telex: 2161867 (HEEG D) Facsimile: (49) 40 2376-2232
SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: (07436) 5-1321 Telex: LABOMETA-B J63428 Facsimile: (07436) 5-1532
(c)1997 by SHARP Corporation Issued July 1996
Reference Code SMT96116

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